Thin film, co-planar integrated circuits employing silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS architectures are typically characterized by the use of either air or (oxide) dielectric to provide lateral isolation between adjacent `mesa` transistors which are formed atop an insulating dielectric (e.g. silicon oxide or sapphire). More particularly, as diagrammatically illustrated in the top view of FIG. 1 and the side view of FIG. 2, a conventional N-channel SOI/SOS thin film MOS transistor structure is typically comprised of a semiconductor (silicon) mesa layer 11, which is disposed atop a substrate-supported dielectric (silicon dioxide) layer 12 and the sidewall perimeter of which is bounded by air or an oxide dielectric layer, shown at 13. This semiconductor mesa structure contains a P-type body/channel region 14 disposed between and immediately contiguous with respective N+ source and drain regions 16 and 18. Overlying the (P-type) channel/body region 14 and extending onto the surrounding support substrate, either coplanar with the top of the mesa as shown in FIG. 2 in the case where the mesa is bounded by an oxide dielectric layer 13, or stepped down to the surface of dielectric layer 12 in the case where the mesa is bounded by air isolation, is a doped polysilicon gate layer 21, insulated from the semiconductor material of the mesa by a thin dielectric layer (e.g. oxide) 22.
Because the surface of P-doped material (here the P-type channel/body region 14) is susceptible to inversion in the presence of ionizing radiation, there is the danger of a leakage path or `parasitic` channel being induced along the body/channel sidewalls 23, 24 between the source and drain regions 16, 18. Moreover, regardless of the potential for exposure to ionizing radiation, the inability of some manufacturing processes to accurately control the channel doping along the edges of the device (beneath the polysilicon gate overlay 21), and the lack of control of electrostatic charge build-up along surface portions 25, 27 of dielectric layer 13 that is immediately adjacent to P-type silicon body 14, may cause the device to suffer extraordinary current leakage in its OFF state.
Another problem associated with this type of architecture is the fact that the body/channel region 14 of the transistor, being situated atop a dielectric layer, is not readily accessible to be terminated to either a Vdd node or, in the case of an N-channel device, a Vss node, so that the potential of the body/channel region effectively `floats`, which can severely degrade the performance of the transistor (e.g. subject the saturation region of the device to the `kink` effect and additionally by permitting parasitic NPN devices to be turned on).